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INTEGRATED CIRCUITS
DATA SHEET
UDA1352TS 48 kHz IEC 60958 audio DAC
Preliminary specification Supersedes data of 2002 May 22 2002 Nov 22
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.2 9.3 9.4 9.5 9.6 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 FEATURES General Control IEC 60958 input Digital sound processing and DAC APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Clock regeneration and lock detection Mute Auto mute Data path Control L3-BUS DESCRIPTION General Device addressing Register addressing Data write mode Data read mode Initialization string I2C-BUS DESCRIPTION Characteristics of the I2C-bus Bit transfer Byte transfer Data transfer Start and stop conditions Acknowledgment Device address Register address Write and read data Write cycle Read cycle 19.2 19.3 19.4 19.5 20 21 22 23 11 11.1 11.2 11.3 11.4 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 13 14 15 16 17 18 19 19.1
UDA1352TS
SPDIF SIGNAL FORMAT SPDIF channel encoding SPDIF hierarchical layers for audio data SPDIF hierarchical layers for digital data Timing characteristics REGISTER MAPPING SPDIF mute setting (write) Power-down settings (write) Volume control left and right (write) Sound feature mode, treble and bass boost settings (write) Mute (write) Polarity (write) SPDIF input settings (write) Interpolator status (read-out) SPDIF status (read-out) Channel status (read-out) FPLL status (read-out) LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
1 1.1 FEATURES General
UDA1352TS
* 2.7 to 3.6 V power supply * Integrated digital filter and Digital-to-Analog Converter (DAC) * 256fs system clock output * 20-bit data path in interpolator * High performance * No analog post filtering required for DAC * Supporting sampling frequencies from 28 up to 55 kHz. 1.2 Control * Bass boost and treble control in L3-bus or I2C-bus mode * Interpolating filter (fs to 64fs) by means of a cascade of a recursive filter and a FIR filter * Fifth-order noise shaper (operating at 64fs) generates the bitstream for the DAC * Filter Stream DAC (FSDAC). 2 APPLICATIONS
* Controlled either by means of static pins, I2C-bus or L3-bus microcontroller interface. 1.3 IEC 60958 input
* Digital audio systems. 3 GENERAL DESCRIPTION
* On-chip amplifier for converting IEC 60958 input to CMOS levels * Lock indication signal available on pin LOCK * Information of the Pulse Code Modulation (PCM) status bit and the non-PCM data detection is available on pin PCMDET * For left and right 40 key channel-status bits available via L3-bus or I2C-bus interface. 1.4 Digital sound processing and DAC
The UDA1352TS is a single-chip IEC 60958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques. A lock indication signal is available on pin LOCK, indicating that the IEC 60958 decoder is locked. A separate pin PCMDET is available to indicate whether or not the PCM data is applied to the input. By default, the DAC output is muted when the decoder is out-of-lock. However, this setting can be overruled in the L3-bus or I2C-bus mode. The UDA1352TS has IEC 60958 input to the DAC only and is in SSOP28 package. Besides the UDA1352TS, the UDA1352HL is also available. The UDA1352HL is the full featured version in LQFP48 package.
* Automatic de-emphasis when using IEC 60958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies * Soft mute by means of a cosine roll-off circuit selectable via pin MUTE, L3-bus or I2C-bus interface * Left and right independent dB linear volume control with 0.25 dB steps from 0 to -50 dB, 1 dB steps to -60, -66 and - dB
4
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm VERSION SOT341-1
UDA1352TS
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
5 QUICK REFERENCE DATA VDDD = VDDA = 3.0 V; IEC 60958 input with fs = 48.0 kHz; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Supplies VDDD VDDA IDDA(DAC) IDDA(PLL) IDDD(C) IDDD P General trst Tamb Vo(rms) Vo (THD+N)/S reset active time ambient temperature - -40 fi = 1.0 kHz tone at 0 dBFS; note 1 fi = 1.0 kHz tone fi = 1.0 kHz tone at 0 dBFS at -40 dBFS; A-weighted fi = 1.0 kHz tone - - - -82 -60 100 110 -77 -52 - - dB dB dB dB 850 - 250 - 900 0.1 - +85 s C mV dB digital supply voltage analog supply voltage analog supply current of DAC analog supply current of PLL digital supply current of core digital supply current power dissipation DAC in playback mode DAC in Power-down mode power-on power-down; clock off 2.7 2.7 - - - - - - - 3.0 3.0 3.3 35 0.3 9 0.3 38 tbf 3.6 3.6 - - - - - - - V V mA A mA mA mA mW mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital-to-analog converter output voltage (RMS value) unbalance of output voltages total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation 950 0.4
S/N cs Note
fi = 1.0 kHz tone; code = 0; A-weighted 95
1. The output voltage of the DAC is proportional to the DAC power supply voltage.
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
6 BLOCK DIAGRAM
UDA1352TS
handbook, full pagewidth
VDDA(DAC) TEST1 2 CLOCK AND TIMING CIRCUIT TEST2 18 VOUTL 15 DAC
Vref VOUTR 19 17 DAC
VSSA(DAC) 14 20
VDDA(PLL) VSSA(PLL) VDDD(C) VSSD(C) DA0 DA1 L3MODE L3CLOCK L3DATA SELSTATIC SELIIC
24 23 6 12
NOISE SHAPER 28 25 10 9 8 26 4 SLICER 13 3 7 21, 22, 27 n.c. 1 16
MGU655
UDA1352TS
INTERPOLATOR L3-BUS OR I2C-BUS INTERFACE 11
AUDIO FEATURE PROCESSOR NON-PCM DATA SYNC DETECTOR
MUTE
SPDIF VDDD VSSD
IEC 60958 DECODER
5
RESET
PCMDET
LOCK
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
7 PINNING SYMBOL PCMDET TEST1 VDDD SELIIC RESET VDDD(C) VSSD L3DATA L3CLOCK L3MODE MUTE VSSD(C) SPDIF VDDA(DAC) VOUTL LOCK VOUTR TEST2 Vref VSSA(DAC) n.c. n.c. VSSA(PLL) VDDA(PLL) DA1 SELSTATIC n.c. DA0 Note 1. See Table 1. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TYPE(1) DO DO DS DID DID DS DGND IIC DIS DIS DID DGND AIO AS AIO DO AIO DID AIO AGND - - AGND AS DISU DIU - DID DESCRIPTION PCM detection indicator output
UDA1352TS
test pin 1; must be left open-circuit in application digital supply voltage I2C-bus or L3-bus mode selection input reset input digital supply voltage for core digital ground L3-bus or I2C-bus interface data input and output L3-bus or I2C-bus interface clock input L3 interface mode input mute control input digital ground for core IEC 60958 channel input analog supply voltage for DAC DAC left channel analog output SPDIF and PLL lock indicator output DAC right channel analog output test pin 2; must be connected to digital ground (VSSD) in application DAC reference voltage analog ground for DAC not connected not connected analog ground for PLL analog supply voltage for PLL A1 device address selection input static pin control selection input not connected (reserved) A0 device address selection input
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
Table 1 Pin types DESCRIPTION digital supply digital ground analog supply analog ground digital input digital Schmitt-triggered input digital input with internal pull-down resistor digital Schmitt-triggered input with internal pull-down resistor digital input with internal pull-up resistor digital Schmitt-triggered input with internal pull-up resistor digital output digital input and output digital Schmitt-triggered input and output input and open-drain output for I2C-bus analog input and output
UDA1352TS
TYPE DS DGND AS AGND DI DIS DID DISD DIU DISU DO DIO DIOS IIC AIO
handbook, halfpage
PCMDET TEST1 VDDD SELIIC RESET VDDD(C) VSSD L3DATA L3CLOCK
1 2 3 4 5 6 7
28 DA0 27 n.c. 26 SELSTATIC 25 DA1 24 VDDA(PLL) 23 VSSA(PLL) 22 n.c.
UDA1352TS
8 9 21 n.c. 20 VSSA(DAC) 19 Vref 18 TEST2 17 VOUTR 16 LOCK 15 VOUTL
MGU654
L3MODE 10 MUTE 11 VSSD(C) 12 SPDIF 13 VDDA(DAC) 14
Fig.2 Pin configuration.
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
8 8.1 FUNCTIONAL DESCRIPTION Clock regeneration and lock detection
handbook, halfpage
UDA1352TS
The UDA1352TS contains an on-board PLL for regenerating a system clock from the IEC 60958 input bitstream. Remark: If there is no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band. When the on-board clock locks to the incoming frequency, the lock indicator bit is set and can be read via the L3-bus or I2C-bus interface. Internally, the PLL lock indication can be combined with the PCM status bit of the input data stream and the status whether any burst preamble is detected or not. By default, when both the IEC 60958 decoder and the on-board clock have locked to the incoming signal and the input data stream is PCM data, pin LOCK will be asserted. However, when the IC is locked but the PCM status bit reports non-PCM data, pin LOCK is returned to LOW level. This combination of the lock status and the PCM detection can be overruled by the L3-bus or I2C-bus register setting. The lock indication output can be used, for example, for muting purposes. The lock signal can be used to drive an external analog muting circuit to prevent out of band noise from becoming audible when the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal). The UDA1352TS has a dedicated pin PCMDET to indicate whether valid PCM data stream is detected or (supposed to be) non-PCM data is detected. 8.2 Mute
1
MGU119
mute factor 0.8
0.6
0.4
0.2
0 0 5 10 15 20 t (ms) 25
Fig.3 Mute as a function of raised cosine roll-off.
8.3
Auto mute
By default, the DAC outputs will be muted until the UDA1352TS is locked, regardless of the level on pin MUTE or the state of bit MT. In this way, only valid data will be passed to the outputs. This mute is done in the SPDIF interface and is a hard mute, not a cosine roll-off mute. If needed, this muting can be bypassed by setting bit MUTEBP = 1 via the L3-bus or I2C-bus interface. As a result, the UDA1352TS will no longer mute during out-of-lock situations.
The UDA1352TS is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC (by pin MUTE or via bit MT in the L3-bus or I2C-bus mode) will result in a soft mute as shown in Fig.3. The cosine roll-off soft mute takes 32 x 32 samples = 23 ms at 44.1 kHz sampling frequency. When operating in the L3-bus or I2C-bus mode, the device will mute on start-up. In the L3-bus or I2C-bus mode, it is necessary to explicitly switch off the mute for audio output by means of bit MT in the device register. In the L3-bus or I2C-bus mode, pin MUTE will at all time mute the output signal. This is in contrast to the UDA1350 and the UDA1351 in which pin MUTE in the L3-bus mode does not have any function.
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
8.4 Data path 8.4.2 AUDIO FEATURE PROCESSOR
UDA1352TS
The UDA1352TS data path consists of the IEC 60958 decoder, the audio feature processor, the digital interpolator and noise shaper and the DACs. 8.4.1 IEC 60958 INPUT
The audio feature processor automatically provides de-emphasis for the IEC 60958 data stream in the static pin control mode and default mute at start-up in the L3-bus or I2C-bus mode. When used in the L3-bus or I2C-bus mode, it provides the following additional features: * Left and right independent volume control * Bass boost control * Treble control * Mode selection of the sound processing bass boost and treble filters: flat, minimum and maximum * Soft mute control with raised cosine roll-off. 8.4.3 INTERPOLATOR
The IEC 60958 decoder features an on-chip amplifier with hysteresis, which amplifies the SPDIF input signal to CMOS level (see Fig.4). All 24 bits of data for left and right are extracted from the input bitstream as well as 40 channel status bits for left and right. These bits can be read via the L3-bus or I2C-bus interface.
handbook, halfpage
The UDA1352TS includes an on-board interpolating filter which converts the incoming data stream from 1fs to 64fs by cascading a recursive filter and a FIR filter.
10 nF SPDIF 13
Table 2
Interpolator characteristics CONDITIONS 0 to 0.45fs >0.55fs 0 to 0.45fs - NOISE SHAPER VALUE (dB) 0.03 -50 114 -5.67
75
PARAMETER
180 pF
Pass-band ripple
UDA1352TS
MGU656
Stop band Dynamic range DC gain 8.4.4
Fig.4
IEC 60958 input circuit and typical application.
The UDA1352TS supports the following sample frequencies and data bit rates: * fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s * fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s * fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s. The UDA1352TS supports timing levels I, II and III, as specified by the IEC 60958 standard. This means that the accuracy of the above mentioned sampling frequencies depends on the timing level I, II or III as mentioned in Section 11.4.1.
The fifth-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted to an analog signal using a filter stream DAC.
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
8.4.5 FILTER STREAM DAC 8.5 Control
UDA1352TS
The Filter Stream DAC (FSDAC) is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC is scaled proportionally with the power supply voltage.
The UDA1352TS can be controlled by means of static pins (when pin SELSTATIC = HIGH), via the I2C-bus (when pin SELSTATIC = LOW and pin SELIIC = HIGH) or via the L3-bus (when pins SELSTATIC and SELIIC are LOW). For optimum use of the features of the UDA1352TS, the L3-bus or I2C-bus mode is recommended since only basic functions are available in the static pin control mode. It should be noted that the static pin control mode and the L3-bus or I2C-bus mode are mutually exclusive. 8.5.1 STATIC PIN CONTROL MODE
The default values for all non-pin controlled settings are identical to the default values at start-up in the L3-bus or I2C-bus mode (see Table 3).
Table 3 PIN
Pin description of static pin control mode NAME VALUE FUNCTION
Mode selection pin 26 Input pins 5 9 10 8 11 RESET L3CLOCK L3MODE L3DATA MUTE 0 1 0 0 0 0 1 Status pins 1 16 Test pins 2 18 TEST1 TEST2 - 0 must be left open-circuit must be connected to VSSD PCMDET LOCK 0 1 0 1 non-PCM data or burst preamble detected PCM data detected clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected clock regeneration and IEC 60958 decoder locked and PCM data detected normal operation reset must be connected to VSSD must be connected to VSSD must be connected to VSSD no mute mute active SELSTATIC 1 select static pin control mode; must be connected to VDDD
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
8.5.2 L3-BUS OR I2C-BUS MODE
UDA1352TS
The L3-bus or I2C-bus mode allows maximum flexibility in controlling the UDA1352TS (see Table 4). It should be noted that in the L3-bus or I2C-bus mode, several base-line functions are still controlled by pins on the device and that, on start-up in the L3-bus or I2C-bus mode, the output is explicitly muted by bit MT via the L3-bus or I2C-bus interface. Table 4 PIN Pin description in the L3-bus or I2C-bus mode NAME VALUE FUNCTION
Mode selection pins 26 4 Input pins 5 8 9 10 11 RESET L3DATA L3CLOCK L3MODE MUTE 0 1 - - - - - 0 1 Status pins 1 16 Test pins 2 18 TEST1 TEST2 - 0 must be left open-circuit must be connected to VSSD PCMDET LOCK 0 1 0 1 non-PCM data or burst preamble detected PCM data detected clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected clock regeneration and IEC 60958 decoder locked and PCM data detected normal operation reset must be connected to the L3-bus must be connected to the SDA line of the I2C-bus must be connected to the L3-bus must be connected to the SCL line of the I2C-bus must be connected to the L3-bus no mute mute active SELSTATIC SELIIC 0 0 1 select L3-bus mode or I2C-bus mode; must be connected to VSSD select L3-bus mode; must be connected to VSSD select I2C-bus mode; must be connected to VDDD
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
9 9.1 L3-BUS DESCRIPTION General
UDA1352TS
Remark: when the device is powered-up, at least one L3CLOCK pulse must be given to the L3-bus interface to wake-up the interface before starting sending to the device (see Fig.5). This is only needed once after the device is powered-up. 9.2 Device addressing
The UDA1352TS has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. The controllable settings are: * Restoring L3-bus default values * Power-on * Selection of filter mode and settings of treble and bass boost * Volume settings left and right * Selection of soft mute via cosine roll-off and bypass of auto mute. The readable settings are: * Mute status of interpolator * PLL locked * SPDIF input signal locked * Audio sample frequency * Valid PCM data detected * Pre-emphasis of the IEC 60958 input signal * Accuracy of the clock. The exchange of data and control information between the microcontroller and the UDA1352TS is LSB first and is accomplished through the serial hardware L3-bus interface comprising the following pins: * L3DATA: data line * L3MODE: mode line * L3CLOCK: clock line. The L3-bus format has two modes of operation: * Address mode * Data transfer mode. The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.5). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data. Basically, two types of data transfers can be defined: * Write action: data transfer to the device * Read action: data transfer from the device.
The device address consists of 1 byte with: * Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table 5) * Address bits 2 to 7 representing a 6-bit device address. The bits 2 and 3 of the address can be selected via the external pins DA0 and DA1, which allows up to 4 UDA1352TS devices to be independently controlled in a single application. The primary address of the UDA1352TS is `001000' (LSB to MSB) and the default address is `011000'. Table 5 Selection of data transfer DOM TRANSFER BIT 0 0 1 0 1 9.3 BIT 1 0 0 1 1 not used not used write data or prepare read read data
Register addressing
After sending the device address (including DOM bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. Basically, there are three methods for register addressing: 1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.5) 2. Addressing for prepare read: bit 0 is logic 1, indicating that data will be read from the register (see Fig.6) 3. Addressing for data read action. Here, the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid.
2002 Nov 22
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L3CLOCK L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 device address 0/1 register address data byte 1 data byte 2
Philips Semiconductors
48 kHz IEC 60958 audio DAC
L3 wake-up pulse after power-up
L3CLOCK
L3MODE device address L3DATA 0 1 0
MGS753
register address
data byte 1
data byte 2
DOM bits
write
Fig.5 Data write mode (for L3-bus version 2).
Preliminary specification
valid/invalid send by the device
MBL565
UDA1352TS
Fig.6 Data read mode.
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
9.4 Data write mode
UDA1352TS
For reading data from a device, the following 6 bytes are involved (see Table 7): 1. One byte with the device address, including `01' for signalling the write action to the device 2. One byte is sent with the register address from which data needs to be read; this byte starts with a `1', which indicates that there will be a read action from the register, followed by seven bits for the source register address in binary format, with A6 being the MSB and A0 being the LSB 3. One byte with the device address preceded by `11' is sent to the device; the `11' indicates that the device must write data to the microcontroller 4. One byte, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1) 5. One byte (from the two bytes), sent by the device to the bus, with the data information in binary format, with D15 being the MSB 6. One byte (from the two bytes), sent by the device to the bus, with the data information in binary format, with D0 being the LSB.
The data write mode is explained in the signal diagram of Fig.5. For writing data to a device, 4 bytes must be sent (see Table 6): 1. One byte starting with `01' for signalling the write action to the device, followed by the device address (`011000' for the UDA1352TS default) 2. One byte starting with a `0' for signalling the write action, followed by 7 bits indicating the destination register address in binary format with A6 being the MSB and A0 being the LSB 3. One data byte (from the two data bytes) with D15 being the MSB 4. One data byte (from the two data bytes) with D0 being the LSB. It should be noted that each time a new destination register address needs to be written, the device address must be sent again. 9.5 Data read mode
To read data from the device, a prepare read must first be done and then data read. The data read mode is explained in the signal diagram of Fig.6. Table 6 BYTE 1 2 3 4 Table 7 BYTE 1 2 3 4 5 6 L3-bus write data L3-BUS MODE address data transfer data transfer data transfer
FIRST IN TIME ACTION BIT 0 device address register address data byte 1 data byte 2 0 0 D15 D7 BIT 1 1 A6 D14 D6 BIT 2 DA0 A5 D13 D5 BIT 3 DA1 A4 D12 D4 BIT 4 1 A3 D11 D3
LAST IN TIME BIT 5 0 A2 D10 D2 BIT 6 0 A1 D9 D1 BIT 7 0 A0 D8 D0
L3-bus read data L3-BUS MODE address data transfer address data transfer data transfer data transfer FIRST IN TIME ACTION BIT 0 device address register address device address register address data byte 1 data byte 2 0 1 1 0 or 1 D15 D7 BIT 1 1 A6 1 A6 D14 D6 BIT 2 DA0 A5 DA0 A5 D13 D5 BIT 3 DA1 A4 DA1 A4 D12 D4 BIT 4 1 A3 1 A3 D11 D3 BIT 5 0 A2 0 A2 D10 D2 BIT 6 0 A1 0 A1 D9 D1 BIT 7 0 A0 0 A0 D8 D0 LAST IN TIME
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
9.6 Initialization string
UDA1352TS
For proper and reliable operation, the UDA1352TS must be initialized in the L3-bus mode. This is required to have the PLL start-up after powering up of the device under all conditions. The initialization string is given in Table 8. Table 8 BYTE 1 2 3 4 5 6 7 8 L3-bus initialization string and set defaults after power-up L3-BUS MODE address data transfer data transfer data transfer address data transfer data transfer data transfer set defaults init string FIRST IN TIME ACTION BIT 0 device address register address data byte 1 data byte 2 device address register address data byte 1 data byte 2 0 0 0 0 0 0 0 0 10.2 BIT 1 1 1 0 0 1 1 0 0 BIT 2 DA0 0 0 0 DA0 1 0 0 Bit transfer BIT 3 DA1 0 0 0 DA1 1 0 0 BIT 4 1 0 0 0 1 1 0 0 BIT 5 0 0 0 0 0 1 0 0 BIT 6 0 0 0 0 0 1 0 0 BIT 7 0 0 0 1 0 1 0 0 LAST IN TIME
10 I2C-BUS DESCRIPTION 10.1 Characteristics of the I2C-bus
The bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to the VDD via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz IC the recommendation for this type of bus from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 to 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy.
One data bit is transferred during each clock pulse (see Fig.7). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. To be able to run on this high frequency all the inputs and outputs connected to this bus must be designed for this high-speed I2C-bus according to specification "The I2C-bus and how to use it", (order code 9398 393 40011).
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.7 Bit transfer on the I2C-bus.
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
10.3 Byte transfer
UDA1352TS
controls the message is the master and the devices which are controlled by the master are the slaves. 10.5 Start and stop conditions
Each byte (8 bits) is transferred with the MSB first (see Table 9). Table 9 MSB 7 10.4 6 5 Byte transfer BIT NUMBER 4 3 2 1 LSB 0
Both data and clock line will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a start condition (S); see Fig.8. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a stop condition (P).
Data transfer
A device generating a message is a transmitter, a device receiving a message is the receiver. The device that
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.8 START and STOP conditions on the I2C-bus.
10.6
Acknowledgment
The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Fig.9). At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.9 Acknowledge on the I2C-bus.
10.7
Device address
10.8
Register address
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with byte 1 transmitted after the start procedure. The device address can be one out of four, being set by pin DA0 and pin DA1. The UDA1352TS acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1352TS device address is shown in Table 10. Table 10 I2C-bus device address DEVICE ADDRESS A6 1 A5 0 A4 0 A3 1 A2 1 A1 DA1 A0 DA0 R/W - 0/1
The register addresses in the I2C-bus mode are the same as in the L3-bus mode. 10.9 Write and read data
The I2C-bus configuration for a write and read cycle are shown respectively in Tables 11 and 12. The write cycle is used to write groups of two bytes to the internal registers for the digital sound feature control and system setting. It is also possible to read these locations for the device status information.
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48 kHz IEC 60958 audio DAC
The I2C-bus configuration for a write cycle is shown in Table 11. The write cycle is used to write the data to the internal registers. The device and register addresses are one byte each, the setting data is always a pair of two bytes. The format of the write cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `1001 110' and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1352TS. 4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1352TS must start. 5. The UDA1352TS acknowledges this register address (A). 6. The microcontroller sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the UDA1352TS. 7. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the UDA1352TS. 8. Finally, the UDA1352TS frees the I2C-bus and the microcontroller can generate a stop condition (P). Table 11 Master transmitter writes to the UDA1352TS registers in the I2C-bus mode. DEVICE ADDRESS 1001 110 R/W 0 A REGISTER ADDRESS ADDR A MS1 DATA 1 A LS1 A MS2 DATA 2(1) A LS2 A MSn DATA n(1) A LSn A P
acknowledge from UDA1352TS
Preliminary specification
UDA1352TS
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 10.11 Read cycle 2002 Nov 22 19 Philips Semiconductors
48 kHz IEC 60958 audio DAC
The read cycle is used to read the data values from the internal registers. The I2C-bus configuration for a read cycle is shown in Table 12. The format of the read cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `1001 110' and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1352TS. 4. After this the microcontroller writes the register address (ADDR) where the reading of the register content of the UDA1352TS must start. 5. The UDA1352TS acknowledges this register address. 6. Then the microcontroller generates a repeated start (Sr). 7. Then the microcontroller generates the device address `1001 110' again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the UDA1352TS. 8. The UDA1352TS sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the microcontroller. 9. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the microcontroller. 10. The microcontroller stops this cycle by generating a negative acknowledge (NA). 11. Finally, the UDA1352TS frees the I2C-bus and the microcontroller can generate a stop condition (P). Table 12 Master transmitter reads from the UDA1352TS registers in the I2C-bus mode. DEVICE R/W ADDRESS S 1001 110 0 A REGISTER ADDRESS ADDR A Sr DEVICE R/W ADDRESS 1001 110 1 A MS1 DATA 1 A LS1 A MS2 DATA 2(1) A LS2 A MSn DATA n(1) A LSn NA P
acknowledge from UDA1352TS Note 1. Auto increment of register address.
acknowledge from master
Preliminary specification
UDA1352TS
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
11 SPDIF SIGNAL FORMAT 11.1 SPDIF channel encoding Table 13 Preambles PRECEDING STATE B M W 11.3
UDA1352TS
CHANNEL CODING 0 1110 1000 1110 0010 1110 0100 1 0001 0111 0001 1101 0001 1011
The digital signal is coded using Bi-phase Mark Code (BMC), which is a kind of phase-modulation. In this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 to one zero-crossing. An example of the encoding is given in Fig.10.
SPDIF hierarchical layers for digital data
handbook, halfpage
clock
The difference with the audio format is that the data contained in the SPDIF signal is not audio but is digital data. When transmitting digital data via SPDIF using the IEC 60958 protocol, the allocation of the bits inside the data word is done as shown in Table 14. Table 14 Bit allocation for digital data
MGU606
data
BMC
FIELD Fig.10 Bi-phase mark encoding. 0 to 3 4 to 7 11.2 SPDIF hierarchical layers for audio data 8 to 11 12 13 From an abstract point of view an SPDIF signal can be represented as in Fig.11. A 2-channel PCM signal can be transmitted as various sequential blocks. Each block in turn consists of 192 frames. Each frame contains two sub-frames, one for each channel. Each sub-frame is preceded by a preamble. There are three types of preambles being B, M and W. Preambles can be spotted easily in an SPDIF stream because these sequences can never occur in the channel parts of a valid SPDIF stream. Table 13 indicates the values of the preambles. A sub-frame in turn contains a single audio sample which may be up to 24 bits wide, a validity bit which indicates whether the sample is valid, a single bit of user data, and a single bit of channel status. Finally, there is a parity bit for this particular sub-frame (see Fig.12). The data bits from 4 to 31 in each sub-frame will be modulated using a BMC scheme. The sync preamble actually contains a violation of the BMC scheme and consequently can be detected easily.
IEC 60958 TIME SLOT BITS preamble auxiliary bits unused data bits 16 bits data user data
DESCRIPTION according to IEC 60958 not used; all logic 0 not used; all logic 0 sections of the digital bitstream according to IEC 60958 sections of the digital bitstream according to IEC 60958 according to IEC 60958 according to IEC 60958 according to IEC 60958
14 to 27 16 bits data 28 29 30 31 validity bit user data channel status bit parity bit
As shown in Table 14 and Fig.13, the non-PCM encoded data bitstreams are transferred within the basic 16 bits data area of the IEC 60958 sub-frames [time-slots 12 (LSB) to 27 (MSB)].
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
handbook, full pagewidth
M channel 1 W
channel 2
B
channel 1
W channel 2
M
channel 1
channel 2
M
channel 1
W
channel 2
sub-frame frame 191
sub-frame frame 191 block
MGU607
frame 0
Fig.11 SPDIF block format.
0 handbook, full pagewidth sync preamble
34 L S B auxiliary
78 L S B audio sample word
27 28 M S B validity flag user data channel status parity bit V U C
31 P
MGU608
Fig.12 Sub-frame format in audio mode.
0 handbook, full pagewidth sync preamble
34 L S B auxiliary
78 L unused S data B
11 12 L S B 16-bit data stream
27 28 M S B validity flag user data channel status parity bit V U C
31 P
MGU609
Fig.13 Sub-frame format in non-PCM mode.
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
11.3.1 FORMAT OF THE BITSTREAM
UDA1352TS
The non-PCM data is transmitted in data bursts, consisting of four 16-bit words (called Pa, Pb, Pc and Pd) followed by the so called burst-payload. The definition of the burst preambles is given in Table 15. Table 15 Burst preamble words PREAMBLE WORD Pa Pb Pc Pd 11.3.2 BURST INFORMATION LENGTH OF THE FIELD 16 bits 16 bits 16 bits 16 bits CONTENTS sync word 1 sync word 2 burst information length code VALUE F872 (hex) 4E1F (hex) see Table 16 number of bits
The burst information given in preamble Pc, meaning the information contained in the data stream, is defined according to IEC 60958 as given in Table 16. Table 16 Fields of burst information in preamble Pc BITS OF Pc 0 to 4 0 1 2 3 4 5 6 7 8 9 10 11 to 13 14 to 31 5 to 6 7 0 0 1 8 to 12 13 to 15 - 0 VALUE NULL data AC-3 data reserved pause MPEG-1 layer 1 data MPEG-1 layer 1, 2 or 3 data or MPEG-2 without extension MPEG-2 with extension reserved MPEG-2, layer 1 low sampling rate MPEG-2, layer 2 or 3 low sampling rate reserved reserved (DTS) reserved reserved error flag indicating an invalid burst-payload data type dependant information bitstream number CONTENTS REFERENCE POINT R - R_AC-3 - bit 0 of Pa bit 0 of Pa bit 0 of Pa bit 0 of Pa - bit 0 of Pa bit 0 of Pa - - - - - - - REPETITION TIME OF DATA BURST IN IEC 60958 FRAMES none 1536 - refer to IEC 60958 384 1152 1152 - 768 2304 - refer to IEC 61937 - - - - - -
error flag indicating a valid burst-payload -
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
11.3.3 MINIMUM BURST SPACING
UDA1352TS
Rise and fall times should be in the range: * 0% to 20% when the data bit is a logic 1 * 0% to 10% when the data bits are two succeeding logic zeros. 11.4.3 DUTY CYCLE
In order to be able to detect the start of a data burst, it is prescribed to have a data-burst which does not exceed 4096 frames. After 4096 frames there must be a synchronization sequence containing 2 frames of complete zero data (being 4 times 16 bits) followed by the preamble burst Pa and Pb. In this way a comparison with a sync code of 96 bits can detect the start of a new burst-payload including the Pc and Pd preambles containing additional stream information. 11.4 11.4.1 Timing characteristics FREQUENCY REQUIREMENTS
The duty cycle (see Fig.14) is defined as: tH Duty cycle = ------------------- x 100% ( tL + tH ) The duty cycle should be in the range: * 40% to 60% when the data bit is a logic 1 * 45% to 55% when the data bits are two succeeding logic zeros.
The SPDIF specification IEC 60958 supports three levels of clock accuracy, being: * Level I, high accuracy: tolerance of transmitting sampling frequency shall be within 50 x 10-6 * Level II, normal accuracy: all receivers should receive a signal of 1000 x 10-6 of nominal sampling frequency * Level III, variable pitch shifted clock mode: a deviation of 12.5% of the nominal sampling frequency is possible. 11.4.2 RISE AND FALL TIMES
handbook, halfpage
tH
tL
90% 50% 10% tr tf
Rise and fall times (see Fig.14) are defined as:
MGU612
tr Rise time = ------------------- x 100% ( tL + tH ) tf Fall time = ------------------- x 100% ( tL + tH )
Fig.14 Rise and fall times.
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12 REGISTER MAPPING Table 17 Register map of control settings (write) REGISTER ADDRESS System settings 01H 03H Interpolator 10H 12H 13H 14H volume control left and right sound feature mode, treble and bass boost mute polarity SPDIF mute setting power-down settings FUNCTION
UDA1352TS
SPDIF input settings 30H SPDIF input settings
Software reset 7FH restore L3-bus default values
Table 18 Register map of status bits (read-out) REGISTER ADDRESS Interpolator 18H SPDIF input 59H 5AH 5BH 5CH 5DH 5EH 5FH FPLL 68H FPLL status SPDIF status channel status bits left [15:0] channel status bits left [31:16] channel status bits left [39:32] channel status bits right [15:0] channel status bits right [31:16] channel status bits right [39:32] interpolator status FUNCTION
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.1 SPDIF mute setting (write)
UDA1352TS
Table 19 Register address 01H BIT Symbol Default BIT Symbol Default 15 - - 7 - - 14 - - 6 - - 13 - - 5 - - 12 - - 4 - - 11 - - 3 - - 10 - - 2 - 0 9 - - 1 - 0 8 MUTEBP 0 0 - 0
Table 20 Description of register bits BIT 15 to 9 8 - MUTEBP SYMBOL reserved Mute bypass setting. A 1-bit value to disable the mute bypass setting. When this mute bypass setting is enabled, then even in out-of-lock situations or non-PCM data detected, the output data will not be suppressed. If this bit is logic 0, then the output will be muted in out-of-lock situations. If this bit is logic 1, then the output will not be muted in out-of-lock situations. Default value 0. reserved When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. DESCRIPTION
7 to 3 2 to 0
- -
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.2 Power-down settings (write)
UDA1352TS
Table 21 Register address 03H BIT Symbol Default BIT Symbol Default 15 - - 7 - - 14 - - 6 - - 13 - - 5 - - 12 - - 4 PON_ SPDIFIN 1 11 - - 3 - 0 10 - - 2 - 0 9 - - 1 EN_INT 1 8 - - 0 PONDAC 1
Table 22 Description of register bits BIT 15 to 5 4 - PON_SPDIFIN SYMBOL reserved Power control SPDIF input. A 1-bit value to enable or disable the power of the IEC 60958 bit slicer. If this bit is logic 0, then the power is off. If this bit is logic 1, then the power is on. Default value 1. When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. Interpolator clock control. A 1-bit value to control the interpolator clock. If this bit is logic 0, then the interpolator clock is disabled. If this bit is logic 1, then the interpolator clock is enabled. Default value 1. Power control DAC. A 1-bit value to switch the DAC into power-on or Power-down mode. If this bit is logic 0, then the DAC is in Power-down mode. If this bit is logic 1, then the DAC is in power-on mode. Default value 1. DESCRIPTION
3 to 2 1
- EN_INT
0
PONDAC
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.3 Volume control left and right (write)
UDA1352TS
Table 23 Register address 10H BIT Symbol Default BIT Symbol Default Table 24 Description of register bits BIT 15 to 8 SYMBOL VCL_[7:0] DESCRIPTION Volume setting left channel. A 8-bit value to program the left channel volume attenuation. The range is 0 to -50 dB in steps of 0.25 dB, to -60 dB in steps of 1 dB, -66 dB and - dB. Default value 0000 0000; see Table 25. Volume setting right channel. A 8-bit value to program the right channel volume attenuation. The range is 0 to -50 dB in steps of 0.25 dB, to -60 dB in steps of 1 dB, -66 dB and - dB. Default value 0000 0000; see Table 25. 15 VCL_7 0 7 VCR_7 0 14 VCL_6 0 6 VCR_6 0 13 VCL_5 0 5 VCR_5 0 12 VCL_4 0 4 VCR_4 0 11 VCL_3 0 3 VCR_3 0 10 VCL_2 0 2 VCR_2 0 9 VCL_1 0 1 VCR_1 0 8 VCL_0 0 0 VCR_0 0
7 to 0
VCR_[7:0]
Table 25 Volume settings left and right channel VCL_7 VCR_7 0 0 0 : 1 1 1 1 : 1 1 1 1 : 1 VCL_6 VCR_6 0 0 0 : 1 1 1 1 : 1 1 1 1 : 1 VCL_5 VCR_5 0 0 0 : 0 0 0 0 : 1 1 1 1 : 1 VCL_4 VCR_4 0 0 0 : 0 0 0 1 : 1 1 1 1 : 1 VCL_3 VCR_3 0 0 0 : 0 1 1 0 : 0 0 1 1 : 1 VCL_2 VCR_2 0 0 0 : 1 0 1 0 : 0 1 0 1 : 1 VCL_1 VCR_1 0 0 1 : 1 0 0 0 : 0 0 0 0 : 1 VCL_0 VOLUME (dB) VCR_0 0 1 0 : 1 0 0 0 : 0 0 0 0 : 1 0 (default) -0.25 -0.5 : -49.75 -50 -51 -52 : -60 -66 - - : -
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.4 Sound feature mode, treble and bass boost settings (write)
UDA1352TS
Table 26 Register address 12H BIT Symbol Default BIT Symbol Default 15 M1 0 7 - - 14 M0 0 6 - - 13 TR1 0 5 - - 12 TR0 0 4 - - 11 BB3 0 3 - - 10 BB2 0 2 - - 9 BB1 0 1 - - 8 BB0 0 0 - -
Table 27 Description of register bits BIT 15 to 14 13 to 12 11 to 8 7 to 0 SYMBOL M[1:0] TR[1:0] BB[3:0] - DESCRIPTION Sound feature mode. A 2-bit value to program the sound processing filter sets (modes) of bass boost and treble. Default value 00; see Table 28. Treble settings. A 2-bit value to program the treble setting. The set is selected by the mode bits. Default value 00; see Table 29. Bass boost settings. A 4-bit value to program the bass boost settings. The set is selected by the mode bits. Default value 0000; see Table 30. reserved
Table 28 Sound feature mode M1 0 0 1 1 M0 0 1 0 1 maximum set flat set (default) minimum set MODE SELECTION
Table 29 Treble settings TR1 0 0 1 1 TR0 0 1 0 1 FLAT SET (dB) 0 0 0 0 MINIMUM SET (dB) 0 2 4 6 MAXIMUM SET (dB) 0 2 4 6
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
Table 30 Bass boost settings BB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FLAT SET (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
UDA1352TS
MINIMUM SET (dB) MAXIMUM SET (dB) 0 2 4 6 8 10 12 14 16 18 18 18 18 18 18 18 0 2 4 6 8 10 12 14 16 18 20 22 24 24 24 24
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.5 Mute (write)
UDA1352TS
Table 31 Register address 13H BIT Symbol Default BIT Symbol Default 15 QMUTE 0 7 - - 14 MT 1 6 - - 13 GS 0 5 - - 12 - - 4 - - 11 - - 3 - - 10 - 0 2 - - 9 - 0 1 - - 8 - 0 0 - -
Table 32 Description of register bits BIT 15 SYMBOL QMUTE DESCRIPTION Quick mute function. A 1-bit value to set the quick mute mode. If this bit is logic 0, then the soft mute mode is selected. If this bit is logic 1, then the quick mute mode is selected. Default value 0. Mute. A 1-bit value to set the mute function. If this bit is logic 0, then the audio output is not muted (unless pin MUTE is logic 1). If this bit is logic 1, then the audio output is muted. Default value 1. Gain select. A 1-bit value to set the gain of the interpolator path. If this bit is logic 0, then the gain is 0 dB. If this bit is logic 1, then the gain is 6 dB. Default value 0. reserved When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. reserved
14
MT
13 12 to 11 10 to 8 7 to 0
GS - - -
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.6 Polarity (write)
UDA1352TS
Table 33 Register address 14H BIT Symbol Default BIT Symbol Default 15 DA_POL_ INV 0 7 - 0 14 - 1 6 - - 13 - - 5 - - 12 - - 4 - - 11 - - 3 - - 10 - - 2 - - 9 - 1 1 - - 8 - 0 0 - -
Table 34 Description of register bits BIT 15 SYMBOL DESCRIPTION
DA_POL_INV DAC polarity control. A 1-bit value to control the signal polarity of the DAC output signal. If this bit is logic 0, then the DAC output is not inverted. If this bit is logic 1, then the DAC output is inverted. Default value 0. - - - - - When writing new settings via the L3-bus or I2C-bus interface, this bit should always remain at logic 1 (default value) to guarantee correct operation. reserved When writing new settings via the L3-bus or I2C-bus interface, this bit should always remain at logic 1 (default value) to guarantee correct operation. When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. reserved
14 13 to 10 9 8 to 7 6 to 0
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.7 SPDIF input settings (write)
UDA1352TS
Table 35 Register address 30H BIT Symbol Default BIT Symbol Default 15 - - 7 - - 14 - - 6 - - 13 - - 5 - - 12 - - 4 - - 11 - - 3 COMBINE_ PCM 1 10 - - 2 BURST_ DET_EN 1 9 - - 1 - 0 8 - - 0 - 0
Table 36 Description of register bits BIT 15 to 4 3 - SYMBOL reserved DESCRIPTION
COMBINE_PCM Combine PCM detection to lock indicator. A 1-bit value to combine the PCM detection status to the lock indicator. If this bit is logic 0, then the lock indicator does not contain PCM detection status. If this bit is logic 1, then the PCM detection status is combined with the lock indicator. Default value 1. BURST_ DET_EN - Burst preamble settings. A 1-bit value to enable auto mute when burst preambles are detected. If this bit is logic 0, then there is no muting. If this bit is logic 1, then there is muting when preambles are detected. Default value 1. When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation.
2
1 to 0
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.8 Interpolator status (read-out)
UDA1352TS
Table 37 Register address 18H BIT Symbol BIT Symbol 15 - 7 - 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 - 10 - 2 MUTE_ STATE 9 - 1 - 8 - 0 -
Table 38 Description of register bits BIT 15 to 3 2 - SYMBOL reserved DESCRIPTION
MUTE_STATE Mute status bit. A 1-bit value to indicate the status of the mute function. If this bit is logic 0, then the audio output is not muted. If this bit is logic 1, then the mute sequence has been completed and the audio output is muted. - reserved
1 to 0
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.9 SPDIF status (read-out)
UDA1352TS
Table 39 Register address 59H BIT Symbol BIT Symbol 15 - 7 - 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 - 10 - 2 BURST_ DET 9 - 1 B_ERR 8 - 0 SPDIFIN_ LOCK
Table 40 Description of register bits BIT 15 to 3 2 - BURST_DET SYMBOL reserved Burst preamble detection. A 1-bit value to signal whether burst preamble words are detected in the SPDIF stream or not. If this bit is logic 0, then no preamble words are detected. If this bit is logic 1, then burst-payload is detected. Bit error detection. A 1-bit value to signal whether there are bit errors detected in the SPDIF stream or not. If this bit is logic 0, then no errors are detected. If this bit is logic 1, then bi-phase errors are detected. DESCRIPTION
1
B_ERR
0
SPDIFIN_LOCK SPDIF lock indicator. A 1-bit value to signal whether the SPDIF decoder block is in lock or not. If this bit is logic 0, then the decoder block is out-of-lock. If this bit is logic 1, then the decoder block is in lock.
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.10 Channel status (read-out) 12.10.1 CHANNEL STATUS BITS LEFT [15:0] Table 41 Register address 5AH BIT Symbol 15 SPDI_ BIT15 7 SPDI_ BIT7 14 SPDI_ BIT14 6 SPDI_ BIT6 13 SPDI_ BIT13 5 SPDI_ BIT5 12 SPDI_ BIT12 4 SPDI_ BIT4 11 SPDI_ BIT11 3 SPDI_ BIT3 10 SPDI_ BIT10 2 SPDI_ BIT2
UDA1352TS
9 SPDI_ BIT9 1 SPDI_ BIT1
8 SPDI_ BIT8 0 SPDI_ BIT0
BIT Symbol
12.10.2 CHANNEL STATUS BITS LEFT [31:16] Table 42 Register address 5BH BIT Symbol 15 SPDI_ BIT31 7 SPDI_ BIT23 14 SPDI_ BIT30 6 SPDI_ BIT22 13 SPDI_ BIT29 5 SPDI_ BIT21 12 SPDI_ BIT28 4 SPDI_ BIT20 11 SPDI_ BIT27 3 SPDI_ BIT19 10 SPDI_ BIT26 2 SPDI_ BIT18 9 SPDI_ BIT25 1 SPDI_ BIT17 8 SPDI_ BIT24 0 SPDI_ BIT16
BIT Symbol
12.10.3 CHANNEL STATUS BITS LEFT [39:32] Table 43 Register address 5CH BIT Symbol BIT Symbol 15 - 7 SPDI_ BIT39 14 - 6 SPDI_ BIT38 13 - 5 SPDI_ BIT37 12 - 4 SPDI_ BIT36 11 - 3 SPDI_ BIT35 10 - 2 SPDI_ BIT34 9 - 1 SPDI_ BIT33 8 - 0 SPDI_ BIT32
12.10.4 CHANNEL STATUS BITS RIGHT [15:0] Table 44 Register address 5DH BIT Symbol 15 SPDI_ BIT15 7 SPDI_ BIT7 14 SPDI_ BIT14 6 SPDI_ BIT6 13 SPDI_ BIT13 5 SPDI_ BIT5 12 SPDI_ BIT12 4 SPDI_ BIT4 11 SPDI_ BIT11 3 SPDI_ BIT3 10 SPDI_ BIT10 2 SPDI_ BIT2 9 SPDI_ BIT9 1 SPDI_ BIT1 8 SPDI_ BIT8 0 SPDI_ BIT0
BIT Symbol
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.10.5 CHANNEL STATUS BITS RIGHT [31:16] Table 45 Register address 5EH BIT Symbol 15 SPDI_ BIT31 7 SPDI_ BIT23 14 SPDI_ BIT30 6 SPDI_ BIT22 13 SPDI_ BIT29 5 SPDI_ BIT21 12 SPDI_ BIT28 4 SPDI_ BIT20 11 SPDI_ BIT27 3 SPDI_ BIT19 10 SPDI_ BIT26 2 SPDI_ BIT18
UDA1352TS
9 SPDI_ BIT25 1 SPDI_ BIT17
8 SPDI_ BIT24 0 SPDI_ BIT16
BIT Symbol
12.10.6 CHANNEL STATUS BITS RIGHT [39:32] Table 46 Register address 5FH BIT Symbol BIT Symbol 15 - 7 SPDI_ BIT39 14 - 6 SPDI_ BIT38 13 - 5 SPDI_ BIT37 12 - 4 SPDI_ BIT36 11 - 3 SPDI_ BIT35 10 - 2 SPDI_ BIT34 9 - 1 SPDI_ BIT33 8 - 0 SPDI_ BIT32
Table 47 Description of register bits (two times 40 bits indicating the left and right channel status) BIT 39 to 36 - 35 to 33 SPDI_BIT[35:33] 32 SPDI_BIT[32] SYMBOL reserved but undefined at present Word length. A 3-bit value indicating the word length; see Table 48. Audio sample word length. A 1-bit value to signal the maximum audio sample word length. If bit 32 is logic 0, then the maximum length is 20 bits. If bit 32 is logic 1, then the maximum length is 24 bits. reserved Clock accuracy. A 2-bit value indicating the clock accuracy; see Table 49. Sample frequency. A 4-bit value indicating the sampling frequency; see Table 50. Channel number. A 4-bit value indicating the channel number; see Table 51. Source number. A 4-bit value indicating the source number; see Table 52. General information. A 8-bit value indicating general information; see Table 53. Mode. A 2-bit value indicating mode 0; see Table 54. Audio sampling. A 3-bit value indicating the type of audio sampling; see Table 55. Software copyright. A 1-bit value indicating software for which copyright is asserted or not. If this bit is logic 0, then copyright is asserted. If this bit is logic 1, then no copyright is asserted. Audio sample word. A 1-bit value indicating the type of audio sample word. If this bit is logic 0, then the audio sample word represents linear PCM samples. If this bit is logic 1, then the audio sample word is used for other purposes. Channel status. A 1-bit value indicating the consumer use of the status block. This bit is logic 0. DESCRIPTION
31 to 30 SPDI_BIT[31:30] 29 to 28 SPDI_BIT[29:28] 27 to 24 SPDI_BIT[27:24] 23 to 20 SPDI_BIT[23:20] 19 to 16 SPDI_BIT[19:16] 15 to 8 7 to 6 5 to 3 2 SPDI_BIT[15:8] SPDI_BIT[7:6] SPDI_BIT[5:3] SPDI_BIT2
1
SPDI_BIT1
0
SPDI_BIT0
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
Table 48 Word length WORD LENGTH SPDI_BIT35 SPDI_BIT34 SPDI_BIT33 SPDI_BIT32 = 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 word length not indicated (default) 16 bits 18 bits reserved 19 bits 20 bits 17 bits reserved 20 bits 22 bits reserved 23 bits 24 bits 21 bits reserved
UDA1352TS
SPDI_BIT32 = 1 word length not indicated (default)
Table 49 Clock accuracy SPDI_BIT29 SPDI_BIT28 0 0 1 1 0 1 0 1 level II level I level III reserved CLOCK ACCURACY
Table 50 Sampling frequency SPDI_BIT27 SPDI_BIT26 SPDI_BIT25 SPDI_BIT24 0 0 0 : 1 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1 44.1 kHz 48 kHz 32 kHz other states reserved SAMPLING FREQUENCY
Table 51 Channel number SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 don't care A (left for stereo transmission) B (right for stereo transmission) C D E F G H I J K CHANNEL NUMBER
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 L M N O
CHANNEL NUMBER
Table 52 Source number SPDI_BIT19 SPDI_BIT18 SPDI_BIT17 SPDI_BIT16 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 don't care 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SOURCE NUMBER
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
Table 53 General information SPDI_BIT[15:8] 000 00000 100 xxxxL 010 xxxxL 110 xxxxL 001 xxxxL 011 1xxxL 101 xxxxL 011 00xxL 011 01xxL 000 1xxxL 000 0001L 111 xxxxL 000 0xxxL Table 54 Mode SPDI_BIT7 0 0 1 1 SPDI_BIT6 0 1 0 1 mode 0 reserved MODE general laser optical products digital-to-digital converters and signal processing products magnetic tape or disc based products FUNCTION
UDA1352TS
broadcast reception of digitally encoded audio signals with video signals broadcast reception of digitally encoded audio signals without video signals musical instruments, microphones and other sources without copyright information analog-to-digital converters for analog signals without copyright information analog-to-digital converters for analog signals which include copyright information in the form of `Cp- and L-bit status' solid state memory based products experimental products not for commercial sale reserved reserved, except 000 0000 and 000 0001L
Table 55 Audio sampling AUDIO SAMPLE SPDI_BIT5 0 0 0 0 : 1 SPDI_BIT4 0 0 1 1 : 1 SPDI_BIT3 SPDI_BIT1 = 0 0 1 0 1 : 1 2 audio samples without pre-emphasis 2 audio samples with 50/15 s pre-emphasis reserved (2 audio samples with pre-emphasis) reserved (2 audio samples with pre-emphasis) other states reserved SPDI_BIT1 = 1 default state for applications other than linear PCM other states reserved
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
12.11 FPLL status (read-out) Table 56 Register address 68H BIT Symbol 15 - 14 - 13 - 12 - 11 - 10 -
UDA1352TS
9 -
8 FPLL_ LOCK 0 -
BIT Symbol
7 -
6 -
5 -
4 VCO_ TIMEOUT
3 -
2 -
1 -
Table 57 Description of register bits BIT 15 to 9 8 7 to 5 4 3 to 0 - FPLL_LOCK - SYMBOL reserved FPLL lock. A 1-bit value that indicates the FPLL status together with bit 4; see Table 58. reserved DESCRIPTION
VCO_TIMEOUT VCO time-out. A 1-bit value that indicates the FPLL status together with bit 8; see Table 58. - reserved
Table 58 Lock status indicators of the FPLL FPLL_LOCK 0 0 1 1 VCO_TIMEOUT 0 1 0 1 FUNCTION FPLL out-of-lock FPLL time-out FPLL in lock FPLL time-out
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Tstg Tamb Vesd Ilu(prot) Isc(DAC) PARAMETER supply voltage storage temperature ambient temperature electrostatic discharge voltage Human Body Model (HBM); note 2 Machine Model (MM); note 3 latch-up protection current short-circuit current of DAC Tamb = 125 C; VDD = 3.6 V Tamb = 0 C; VDD = 3 V; note 4 output short-circuited to VSSA(DAC) output short-circuited to VDDA(DAC) Notes 1. All VDD and VSS connections must be made to the same power supply. 2. JEDEC class 2 compliant. 3. JEDEC class B compliant. 4. DAC operation after short-circuiting cannot be warranted. 14 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air - - note 1 CONDITIONS MIN. 2.7 -65 -40 -2000 -200 -
UDA1352TS
MAX. 5.0 +125 +85 +2000 +200 200 20 100 V
UNIT C C V V mA mA mA
VALUE 110
UNIT K/W
15 CHARACTERISTICS VDDD = VDDA = 3.0 V; IEC 60958 input with fs = 48.0 kHz; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Supplies; note 1 VDDA VDDA(DAC) VDDA(PLL) VDDD VDDD(C) IDDA(DAC) IDDA(PLL) IDDD(C) IDDD P analog supply voltage analog supply voltage for DAC analog supply voltage for PLL digital supply voltage digital supply voltage for core analog supply current of DAC analog supply current of PLL digital supply current of core digital supply current power dissipation DAC in playback mode DAC in Power-down mode power-on power-down; clock off 2.7 2.7 2.7 2.7 2.7 - - - - - - - 3.0 3.0 3.0 3.0 3.0 3.3 35 0.3 9 0.3 38 tbf 3.6 3.6 3.6 3.6 3.6 - - - - - - - V V V V V mA A mA mA mA mW mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
SYMBOL Digital inputs VIH VIL ILI Ci Rpu(int) Rpd(int) VOH VOL IO(max) Vo(rms) Vo Vref (THD+N)/S
PARAMETER
CONDITIONS
MIN. - - - - 33 33
TYP.
MAX.
UNIT
HIGH-level input voltage LOW-level input voltage input leakage current input capacitance internal pull-up resistance internal pull-down resistance IOH = -2 mA IOL = 2 mA
0.8VDDD -0.5 - - 16 16
VDDD + 0.5 V +0.2VDDD 10 10 78 78 - 0.4 - 950 0.4 V A pF k k
Digital outputs HIGH-level output voltage LOW-level output voltage maximum output current 0.85VDDD - - - fi = 1.0 kHz tone at 0 dBFS; note 3 fi = 1.0 kHz tone measured with respect to VSSA fi = 1.0 kHz tone at 0 dBFS - -82 -60 100 110 -77 -52 - - 3.3 - - dB dB dB dB at -40 dBFS; A-weighted - fi = 1.0 kHz tone; code = 0; 95 A-weighted fi = 1.0 kHz tone - 0.2 - - 850 - - 3 V V mA
Digital-to-analog converter; note 2 output voltage (RMS value) unbalance of output voltages reference voltage total harmonic distortion-plus-noise to signal ratio signal-to-noise ratio channel separation 900 0.1 mV dB V
0.45VDDA 0.50VDDA 0.55VDDA
S/N cs SPDIF input Vi(p-p) Ri Vhys Notes
AC input voltage (peak-to-peak value) input resistance hysteresis voltage
0.5 6 40
V k mV
1. All supply pins VDD and VSS must be connected to the same external power supply unit. 2. When the DAC must drive a higher capacitive load (above 50 pF), a series resistor of 100 must be used to prevent oscillations in the output stage of the operational amplifier. 3. The output voltage of the DAC is proportional to the DAC power supply voltage.
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
16 TIMING CHARACTERISTICS VDDD = VDDA = 2.4 to 3.6 V; Tamb = -40 to +85 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Device reset trst PLL lock time tlock time-to-lock fs = 32.0 kHz fs = 44.1 kHz fs = 48.0 kHz L3-bus microcontroller interface; see Figs 15 and 16 Tcy(CLK)(L3) tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D t(stp)(L3) tsu(L3)DA th(L3)DA td(L3)R tdis(L3)R L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time in address mode L3MODE hold time in address mode L3MODE set-up time in data transfer mode L3MODE hold time in data transfer mode L3MODE stop time in data transfer mode L3DATA set-up time in address and data transfer mode L3DATA hold time in address and data transfer mode L3DATA delay time in data transfer mode L3DATA disable time for read data 500 250 250 190 190 190 190 190 190 30 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 50 50 ns ns ns ns ns ns ns ns ns ns ns ns - - - 85.0 63.0 60.0 - - - ms ms ms reset active time - 250 - s PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I2C-bus microcontroller interface; see Fig 17 fSCL tLOW tHIGH tr tf tHD;STA tSU;STA tSU;STO tBUF SCL clock frequency SCL LOW time SCL HIGH time rise time SDA and SCL fall time SDA and SCL hold time start condition set-up time START condition set-up time STOP condition bus free time between a STOP and START condition note 1 note 1 0 1.3 0.6 20 + 0.1Cb 20 + 0.1Cb 0.6 0.6 0.6 1.3 400 - - 300 300 - - - - kHz s s ns ns s s s s
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
SYMBOL tSU;DAT tHD;DAT tSP Cb Note data hold time
PARAMETER data set-up time pulse width of spikes to be suppressed by the input filter capacitive load for each bus line
CONDITIONS 0 0
MIN. 100 - - - -
TYP. - -
MAX.
UNIT ns s ns pF
50 400
1. Cb is the total capacity of one bus line.
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.15 Timing for address mode.
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352TS
handbook, full pagewidth
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK
th(L3)DA L3DATA write
tsu(L3)DA
BIT 0
BIT 7
L3DATA read td(L3)R tdis(L3)R
MBL566
Fig.16 Timing for data transfer mode.
handbook, full pagewidth
SDA tf
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL tHD;STA tSU;STA tSU;STO
S
tHD;DAT
tHIGH
Sr
P
S
MSC610
Fig.17 Timing of the I2C-bus transfer.
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L1 VDDA BLM31A601S S7 C2 100 F (16 V) C3 100 nF (50 V) VSSA(PLL) VDDA(DAC) C13 100 nF (50 V) VSSA(DAC) 14 20 23 VDDA(PLL) TEST2 18 5 VDDD
1 2 3
17 APPLICATION INFORMATION
Philips Semiconductors
48 kHz IEC 60958 audio DAC
RST NORM n.c. n.c. 22 n.c. 27 19 Vref C15 100 nF (50 V) VOUTL C17 47 F (16 V) C14 10 F (16 V) R5 R6 10 k 100 X2 left_out
L3 BLM31A601S VDDA C12 100 F (16 V)
RESET 21
24
L3CLOCK L3MODE L3DATA
9 10 8
15
17 X1 R10 75 C6 180 pF (50 V) C7 10 nF (50 V) SPDIF 13
VOUTR
C18 47 F (16 V)
R7 R8 10 k 100
X3 right_out
UDA1352TS
Fig.18 Application diagram.
handbook, full pagewidth
46
L2 VDDD R4 VDDD 1 +3 V C20 100 F (16 V) GND
VDDD(C) C4 100 F (16 V)
6
BLM31A601S
11
MUTE
VDDD
C5 VSSD(C) 100 nF 12 (50 V) 26 VDDD 3 7 1 VDDA VDDD PCMDET R9 1 k HLMP-1385 (2x) D2 16 LOCK R3 1 k D1 28 DA0 25 DA1 4 SELIIC VDDD SELSTATIC
1 2 3
S2 mute no mute VDDD
1 2 3
S1 STATIC L3-bus or I2C-bus
S4
1 2 3
C10 100 F (16 V)
C11 100 nF (50 V)
VSSD
I2C-bus L3-bus
VDDD S6 1 0
C21 100 F (16 V)
1 2 3
S5 1 0
VDDD
1 2 3
Preliminary specification
MGU657
UDA1352TS
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
18 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
UDA1352TS
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
19 SOLDERING 19.1 Introduction to soldering surface mount packages
UDA1352TS
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 19.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 19.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
19.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
UDA1352TS
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
20 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
UDA1352TS
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 21 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 Nov 22
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Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
23 PURCHASE OF PHILIPS I2C COMPONENTS
UDA1352TS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2002 Nov 22
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/02/pp52
Date of release: 2002
Nov 22
Document order number:
9397 750 10469

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